1. Field of the Invention
The present invention relates generally to semiconductor packaging, and more particularly to a packaging configuration capable of carrying a high density of transmission line structures that can be bonded directly to a printed wiring board.
2. Description of the Related Art
There are a very large number of integrated circuit packages on the market. Generally speaking the packaging process is a separate activity from production of the active die, and typically carried out by a packaging contractor. Packages are purchased by assembly contractors where product circuit boards are completed. Since these assembly contractors generally lack the technology to attach silicon die directly to a circuit board packaging contractors have provided this service. Attaching the silicon die is often done by ultrasonic wire bonding of pads on the integrated circuit (IC) to a lead frame. A hermetically sealed package, frequently plastic, is used to enclose the IC. In a final step the leads are cut and formed into pins forming the classic dual inline package as illustrated in block diagram 100 of FIG. 1. As IC technology has progressed there has been a move towards surface mounting packages with a high density of connections at the package periphery, such as the quad flat pack outline illustrated in block diagram 106 of FIG. 2.
Further increases in pin counts have forced two major changes. Firstly, there is a need for more than one row of contacts at the periphery of the device, as otherwise the pitch of the connections is too small for a reasonably strong bond to a circuit board to be formed by wire bonding processes. Secondly, the number of contacts to the chip is so large that wire bonding is becoming uneconomical. This has led to the development of the ball grid array and the flip chip packaging designs. Both technologies use solder balls, which are connected to the package or die. Heat is used to reflow the solder to make contact to the mating part, either a printed circuit board (PCB) or an interposer.
Because of the large thermal expansion difference between silicon and typical circuit boards, most packages use a substrate or interposer to redistribute the bonds from the die to the solder balls. More advanced packages may include several layers of wiring in the interposer along with integrated passives. The connection between the interposer (which is usually made of a laminate material) and the die has to take account of thermal expansion mismatch between the silicon and the interposer. There are a large number of ways of making the connection ranging from the traditional wirebond, through flip chip connections via solder balls as mentioned above (using an underfill adhesive to relieve the thermally induced strain in the balls), to micromachined fingers that can be bonded via conductive adhesive to the interposer. The purpose of the interposer is partly to provide for redistribution of wires, but also it allows a package with thermal expansion coefficient similar to the PCB to be provided to the assembly house. Therefore, the burden of accommodating the thermal mismatch between the die and the laminate is borne by the packager, not by the assembly contractor who generally has neither the skills nor the time to consider such matters.
A typical modem package is the flip-chip ball grid array (FCBGA) illustrated as block diagram 110 of FIG. 3. The FCBGA consists of a ceramic or plastic substrate that has an area array of solder balls 118 (typically composed of an eutectic alloy of tin and lead) for attachment to a circuit board. The semiconductor chip 112 is connected to the substrate 114 through solder bumps 116 in conjunction with an epoxy underfill between the chip 112 and the substrate 114.
Unfortunately, the technology available to process wiring on laminate material is less sophisticated than that used to develop the active silicon die. The thermal stability, dimensional stability, tendency to outgas contaminants, and other properties of laminate restrict the wiring that can be applied. However, one problem with a package using a non-laminate interposer is that the package must accommodate the thermal expansion differences between the selected interposer and a PCB. Most hard materials useful for high-precision processing have thermal expansion coefficients much less than that of the printed circuit board, thereby making the materials unsuitable as an interposer.
Another problem also related to the production of high speed integrated circuits is that the delays in on-die interconnects continue to increase as semiconductor device features shrink. In turn, the lines used for global interconnects continue to shrink in size along with the scaling of the chip. Because of the increasing RC delay (which is only partially offset by the shift to copper conductors and low-k dielectrics), a large number of repeaters, i.e., non-inverting buffer amplifiers, must be inserted into the global interconnect lines. These repeaters recover the integrity of the signal but at a cost of the gate delay in the repeater. As a result the speed of propagation in on-chip wires is expected to be steady at 40 ps/mm length in optimally repeatered wires. FIG. 4 illustrates graph 120 displaying the generally known relationship between relative signal delay vs. the process technology node. Each curve has been normalized to show the relative change in signal delay for different classes of interconnect. Line 122 represents the relative delays of global interconnects without repeaters, line 124 represents global interconnects with repeaters, line 126 represents local interconnects and line 128 represents gate delay (fan out 4) The gate delay represents the delay due to the transistor switching speed. Local interconnects are used to span clusters of a few transistors and are short compared with global interconnects. Moreover, the repeaters themselves are difficult to fabricate since connections must be made from top level metal to the transistor. In addition, the repeaters consume considerable power.
The velocity of wave propagation in an LC transmission line made in surroundings with relative dielectric constant ∈r=2.7 is about 5 ps/mm, eight times faster than that in a repeatered line; but such lines must have a total resistance significantly less than the impedance of the transmission line. The practical limits on this impedance are 30-100 ohms. From this, it can be shown that a copper conductor 2 cm long should be at least 2.7 microns per side at low frequencies, rising to at least 5 microns at about 10 gigahertz (GHz) because of skin effects. FIG. 5 illustrates graph 130 representing the critical wire size for a square copper wire 2 cm long where Z=60xcexa9. Furthermore, to make a transmission line, the conductor must be in a well-controlled relationship with a grounded surface, and the necessary space between the conductor and this grounded surface further increase the space needed for the whole transmission line. Standard IC fabrication techniques are not well suited for these large structures because a considerable metal and dielectric thickness (xcx9c10 xcexcm) is needed. Many IC techniques are optimized for the 0.1-1 xcexcm thickness regime. Thicker layers may be better fabricated by lower cost techniques. However, the density of such interconnects, and the requirements for reasonable precision of spacing between the conductor and ground return path, means that printed circuit board technology is also unsuitable. The correct length scale lies between the PCB and high-end IC technology, in the length scales associated with magnetic disk head technology and micro-machine production.
Naeemi in xe2x80x9cPerformance improvement using on-board wires for on-chip interconnects,xe2x80x9d IEEE, October 2000, pp. 325-328, has shown that for future microprocessors the number of global interconnects longer than a few cm is limited to a few thousand. In a die projected to be as large as 40 mm per side, the number of lines pins needed to move all wires longer than longer than 3 cm off the die can be estimated at about 8000. This is a large number, but the same roadmaps show that such a die will have about 4000 power pins and 2000 I/O pins.
As a result, there is a need to solve the problems of the prior art to provide an interposer capable of carrying a high density of transmission line structures and accommodating a thermal expansion mismatch in order to bond the interposer to a printed circuit board.
Broadly speaking, the present invention fills these needs by providing a method for packaging an integrated circuit and packaging configuration where an interposer is enabled to carry a high density of transmission line structures. Additionally, the packaging configuration is capable of being bonded directly to a printed wiring board in a manner where a thermal expansion mismatch is accommodated. It should be appreciated that the present invention can be implemented in numerous ways, including as an apparatus, a system, a device, or a method. Several inventive embodiments of the present invention are described below.
In one embodiment, an integrated circuit package is provided. The apparatus includes a semiconductor having first and second sides, where the first side defines an inner region and peripheral region. The inner region is surrounded by the peripheral region. An interposer having a substantially similar coefficient of thermal expansion to the semiconductor is included. A dielectric region surrounding the interposer is also included. The dielectric region is configured to be partially elastic. A plurality of posts extends transversely through the dielectric region. The post have first and second ends where the first ends are configured to be attached to the peripheral region of the semiconductor chip. The second ends of the posts are configured to be attached to an external assembly, wherein the posts are able to absorb stress due to a thermal expansion mismatch between the external assembly and the interposer.
In another embodiment, a package for mounting an integrated circuit to a circuit board is provided. The package includes an integrated circuit and an interposer bonded to an inner region of the integrated circuit. A partially elastic dielectric medium surrounds the interposer. The elastic dielectric medium is configured to accommodate a plurality of posts. The posts have first and second ends, where the first ends of the posts are bonded to a peripheral region of the integrated circuit. The second ends of the posts are configured to be bonded to the circuit board.
In yet another embodiment, a method for fabricating an integrated circuit package is provided. The method initiates with providing a first and second wafer, where the first wafer defines a plurality of semiconductor chips and the second wafer defines a plurality of interposer regions. The interposer regions have a substantially similar coefficient of thermal expansion to the semiconductor chips and each die of the first wafer is the same size as a corresponding die of the second wafer. Next, each of the interposer regions is surrounded with a flexible dielectric material. Then, a plurality of post are embedded transversely through the flexible dielectric material, where the posts have first and second ends. Then, the first wafer is bonded to the second wafer. The wafer bonding includes attaching an inner region of each semiconductor chip of the first wafer to a corresponding interposer of the second wafer and attaching the first ends of the posts to corresponding peripheral pads of the semiconductor chip. Next, each bonded die of the first and second wafers is singulated. Then the second ends of the posts are affixed to an external assembly.
In still another embodiment, a method for bonding two silicon die for subsequent bonding to a circuit board is provided. The method initiates with providing a first and second die with substantially similar coefficients of thermal expansion, where the first die is an integrated circuit and the second die is configured as an interposer. Next, a trench is formed surrounding the interposer. Then, the trench is filled with a partially elastic insulating material. Next, a plurality of holes is established in the trench. Posts are then created in each of the holes, where the posts have first and second ends. The first and second die are bonded to each other such that the interposer is bonded to an inner region of the first die and the first ends of the posts are bonded to peripheral contact pads of the first die. The second ends of the posts are then affixed to the circuit board.
In still yet another embodiment, a method for fabricating an integrated circuit package is provided. The method initiates with providing a plurality of singulated semiconductor chips. Then, a wafer defining a plurality of interposer regions is provided. The interposer regions have a substantially similar coefficient of thermal expansion to the semiconductor chips. Next, each of the interposer regions is surrounded with a flexible dielectric material. Then, a plurality of posts are embedded transversely through the flexible dielectric material where the posts have first and second ends. The semiconductor chips are then bonded to the wafer. The bonding includes attaching an inner region of each semiconductor chip to a corresponding interposer of the second wafer, and attaching the first ends of the posts to corresponding peripheral pads of the semiconductor chip. Next, each of the interposers of the wafer are singulated. Then, the second ends of the posts are affixed to an external assembly.
The advantages of the present invention are numerous. Most notably, the posts are able to deform due to the relatively elastic medium surrounding them. Therefore, excessive stress because of the thermal expansion mismatch is avoided. In addition, because the interposer and the active die are made of similar material, it is possible to use high densities of bonds without the need for underfill material. Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.